datasheet loco? pll cloc k multiplier ics512 idt? / ics? loco? pll clock multiplier 1 ics512 rev h 051310 description the ics512 is the most cost effective way to generate a high-quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. the name loco stands for low cost oscillator, as it is designed to replac e crystal oscillators in most electronic systems. using phase-locked-loop (pll) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 200 mhz. with a reference output, this chip plus an inexpensive crystal can replace two oscillators stored in the chip?s rom is the ability to generate nine different multiplication fact ors, allowing one chip to output many common frequencies (see table on page 2). this product is intended for clock generation. it has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. for applications which require defined input to output skew, use the ics570b. features ? packaged as 8-pin soic or die ? pb (lead ) free package ? upgrade of popular ics502 with: ? changed multiplier table ? higher operating frequncies ? zero ppm multip lication error ? easy to cascade with other 5xx series ? input crystal frequency of 5 - 27 mhz ? input clock frequency of 2 - 50 mhz ? output clock frequencies up to 200 mhz ? compatible with all popular cpus ? duty cycle of 45/55 up to 200 mhz ? mask option for nine selectable frequencies ? operating voltages of 3.0 to 5.5 v ? industrial temperature version available ? advanced, low power cmos process block diagram pll clock synthesis and control circuitry crystal or clock input vdd crystal oscillator s1, s0 x1/iclk x2 2 clk gnd optional crystal capacitors ref
ics512 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 2 ics512 rev h 051310 pin assignment clock output table 0 = connect directly to ground 1 = connect directly to vdd m = leave unconnected (floating) common output frequencies example (mhz) note that all of the above are achieved using a common, inexpensive 10 mhz to 25 mhz crystal. consult idt on how to achieve other output frequncies. x1/iclk vdd gnd s1 ref s0 clk x2 1 2 3 4 8 7 6 5 8-pin (150 mil) soic s1 s0 clk 00 4x input 0 m 5.333x input 01 5x input m 0 2.5x input mm 2x input m 1 3.333x input 10 6x input 1m 3x input 11 8x input output 20 24 30 32 33.33 37.5 40 48 50 60 64 input 10 12 10 16 16.66 15 10 12 20 10 16 selection (s1, s0) m,m m,m 1, m m,m m,m m,0 0,0 0,0 m,0 1,0 0,0 output 66.66 72 75 80 83.33 90 100 120 125 133.3 150 input 20 12 25 10 25 15 20 15 25 25 25 selection (s1, s0) m,1 1,0 1,m 1,1 m,1 1,0 0,1 1,1 0,1 0,m 1,0
ics512 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 3 ics512 rev h 051310 pin descriptions pin number pin name pin type pin description 1 xi/iclk input crystal connection or clock input. 2 vdd power connect to +3.3 v or +5 v. 3 gnd power connect to ground. 4 nc ref buffered crystal oscillator output clock. 5 clk output clock output per table above. 6 s0 tri-level input mulitplier select pi n 0. connect to gnd or vdd or float. 7 s1 tri-level input mulitplier select pi n 1. connect to gnd or vdd or float. 8 x2 output crystal connection. leave unconnected for clock input.
ics512 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 4 ics512 rev h 051310 external components decoupling capacitor as with any high-performance mixed-signal ic, the ics512 must be isolated from system power supply noise to perform optimally. a decoupling capacitor of 0.01f must be connected between vdd and gnd. it must be connected close to the ics512 to minimize lead inductance. no external power supply filtering is required for the ics512. series termination resistor a 33 ? terminating resistor can be used next to the clk pin. the total on-chip capacitance is approximately 12 pf. a parallel resonant, fundamental mode crystal should be used. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors, if needed, must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -12 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each crystal capacitor would be 8 pf [(16-12) x 2] = 8. absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics512. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature (commercial) 0 +70 c ambient operating temperature (industrial) -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +5.0 v
ics512 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 5 ics512 rev h 051310 dc electrical characteristics vdd=3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise ac electrical characteristics vdd=3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise note: the phase relationship between intput and output clocks can change at power up. for a fixed phase relationship, see the ics570 or the ics527. parameter symbol conditions min. typ. max. units operating voltage vdd 3 5.5 v input high voltage, iclk only v ih iclk (pin 1) (vdd/2)+1 vdd/2 v input low voltage, iclk only v il iclk (pin 1) vdd/2 (vdd/2)-1 v input high voltage v ih s0, s1 vdd-0.5 v input low voltage v il s0, s1 0.5 v output high voltage, cmos high v oh i oh = -8 ma vdd-0.4 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v idd operating supply current, 20 mhz crystal no load, 100 mhz 9 ma short circuit current clk output + 70 ma input capacitance, s1, s0 pins 6, 7 4 pf parameter symbol conditions min. typ. max. units input frequency, crystal input f in 527mhz input frequency, clock input f in 250mhz output frequency, vdd = 4.5 to 5.5 v f out 0 to +70c 14 200 mhz -40 to +85c 14 160 mhz output frequency, vdd = 3.0 to 3.6 v f out 0 to +70c 14 160 mhz -40 to +85c 14 145 mhz output clock rise time t or 0.8 to 2.0 v 1 ns output clock fall time t of 2.0 to 8.0v 1 ns output clock duty cycle t od at vdd/2 45 49-51 55 % absolute clock period jitter t ja deviation from mean + 200 ps one sigma clock period jitter t js 80 ps
ics512 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 6 ics512 rev h 051310 package outline and package dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) assumes no responsibility for either its use or for the infringem ent of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature 512mlf 512mlf tubes 8-pin soic 0 to +70 c 512mlft 512mlf tape and reel 8-pin soic 0 to +70 c 512milf 512milf tubes 8-pin soic -40 to +85 c 512MILFT 512milf tape and reel 8-pin soic -40 to +85 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 *for reference only. controlling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 0 8 0 8
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